REDDY, A Supraja, REHMAN, B. Khaleelu, ANURADHA, P., SIVA REDDY, K. Venkata, BASHA, Mudasar und NASAR, Mohammed Abdul, 2025. Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures. In: . 3 September 2025.
Elsevier - Harvard (with titles)Reddy, A.S., Rehman, B.K., Anuradha, P., Siva Reddy, K.V., Basha, M., Nasar, M.A., 2025. Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures, in: . https://doi.org/10.1109/ICIMIA67127.2025.11200640
American Psychological Association 7th editionReddy, A. S., Rehman, B. K., Anuradha, P., Siva Reddy, K. V., Basha, M., & Nasar, M. A. (2025, September 3). Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures. https://doi.org/10.1109/ICIMIA67127.2025.11200640
Springer - Basic (author-date)Reddy AS, Rehman BK, Anuradha P, Siva Reddy KV, Basha M, Nasar MA (2025) Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures
Juristische Zitierweise (Stüber) (Deutsch)Reddy, A Supraja/ Rehman, B. Khaleelu/ Anuradha, P./ Siva Reddy, K. Venkata/ Basha, Mudasar/ Nasar, Mohammed Abdul, Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures, 2025, .