• Designing a High-Speed, Low-Ar...

Treffer: Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures

Title:
Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI Architectures
Authors:
Reddy, A Supraja, Rehman, B. Khaleelu, Anuradha, P., Siva Reddy, K. Venkata, Basha, Mudasar, Nasar, Mohammed Abdul
Source:
2025 4th International Conference on Innovative Mechanisms for Industry Applications (ICIMIA) Innovative Mechanisms for Industry Applications (ICIMIA), 2025 4th International Conference on. :98-104 Sep, 2025
Relation:
2025 4th International Conference on Innovative Mechanisms for Industry Applications (ICIMIA)
Database:
IEEE Xplore Digital Library