• Hybrid Interconnect and Interm...

Treffer: Hybrid Interconnect and Intermediate Memory-Based 2.5D NoC Architecture for High Performance Computing Applications

Title:
Hybrid Interconnect and Intermediate Memory-Based 2.5D NoC Architecture for High Performance Computing Applications
Authors:
Kondoth, Lashmi, Shankaran, Rajan, Sheng, Quan Z., Kuantama, Endrowednes
Source:
2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) MCSOC Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2025 IEEE 18th International Symposium on. :131-134 Dec, 2025
Relation:
2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
Database:
IEEE Xplore Digital Library