PAVITRA, Y. J. und MANIKANDAN, J., 2025. Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. Neural Computing & Applications. 21 November 2025. Vol. 37, no. 33, p. 27747-27757. DOI 10.1007/s00521-025-10981-5.
Elsevier - Harvard (with titles)Pavitra, Y.J., Manikandan, J., 2025. Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. Neural Computing & Applications 37, 27747-27757. https://doi.org/10.1007/s00521-025-10981-5
American Psychological Association 7th editionPavitra, Y. J., & Manikandan, J. (2025). Design of compressor-based multipliers using simulated annealing for arithmetic logic unit. Neural Computing & Applications, 37(33), 27747-27757. https://doi.org/10.1007/s00521-025-10981-5
Springer - Basic (author-date)Pavitra YJ, Manikandan J (2025) Design of compressor-based multipliers using simulated annealing for arithmetic logic unit.. Neural Computing & Applications 37:27747-27757. https://doi.org/10.1007/s00521-025-10981-5
Juristische Zitierweise (Stüber) (Deutsch)Pavitra, Y. J./ Manikandan, J., Design of compressor-based multipliers using simulated annealing for arithmetic logic unit., Neural Computing & Applications 2025, 27747-27757.