Treffer: Design of compressor-based multipliers using simulated annealing for arithmetic logic unit.

Multipliers have complex structures and optimization of multiplier designs plays an important role in improving the performance parameters like area, power, and delay. A novel 4:2 counter-based compressor multipliers with pre-processing are proposed for the design of arithmetic and logic unit (ALU). Metaheuristics are widely used in finding various design alternatives to overcome the limitation of traditional approaches for circuit design. Arithmetic and logic unit is an important part of processing unit capable of performing various arithmetic and logical operations. Population-based simulated annealing is used for the design of ALU and two benchmark ALUs from LGSynth'91 are designed. Proposed work reduced the gate count by maximum of 51.83% and transistor count by 92.03% over baseline ALUs reported in literature. The flexibility to use different combination of resources allows us to propose various design alternatives. Functional units of proposed ALUs are designed using various resource types. A graphical user interface is developed for generation of Verilog scripts and test bench for verification of functional blocks. Proposed ALUs are synthesized on FPGA and Cadence Genus-90 nm standard cell library to compare with existing designs. With a speed increase of up to 54.95%, the proposed ALU outperformed traditional multiplier-based ALUs. Additionally, the suggested compressor-based ALU performed better, using 7.4% less power and increasing speed by 14.23%. [ABSTRACT FROM AUTHOR]