UB FFM: Suchergebnisse - High Performance Embedded Architectures and Compilers

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High-Performance Embedded Architecture and Compilation Roadmap
Transactions on high performance embedded architectures and compilers 1
De Bosschere, K. ; Luk, W. ; Martorell, X. ; et al.
LECTURE NOTES IN COMPUTER SCIENCE. (4050):5-32

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2

Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems
High performance embedded architectures and compilers; Transactions on high-performance embedded architectures and compilers II
Bhadauria, M. ; McKee, S.A. ; Singh, K. ; et al.
LECTURE NOTES IN COMPUTER SCIENCE. (5470):65-84

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3

Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
High performance embedded architectures and compilers; HiPEAC 2007
Bhadauria, M. ; McKee, S. A. ; Singh, K. ; et al.
LECTURE NOTES INCOMPUTER SCIENCE. (4367):23-37

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4

Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems
Transactions on high performance embedded architectures and compilers 1
Geiger, M. J. ; McKee, S. A. ; Tyson, G. S.
LECTURE NOTES IN COMPUTER SCIENCE. (4050):54-73

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5

Software Defined Radio - A High Performance Embedded Challenge
High performance embedded architectures and compilers
Lee, H. ; Lin, Y. ; Harel, Y. ; et al.
LECTURE NOTES IN COMPUTER SCIENCE. (3793):6-28

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6

Compiler-Assisted Memory Encryption for Embedded Processors
High performance embedded architectures and compilers; Transactions on high-performance embedded architectures and compilers II
Nagarajan, V. ; Gupta, R. ; Krishnaswamy, A.
LECTURE NOTES IN COMPUTER SCIENCE. (5470):23-44

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7

Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture
High performance embedded architectures and compilers: HiPEAC 2008
Sarkar, S. ; Tullsen, D.M.
LECTURE NOTES IN COMPUTER SCIENCE. (4917):353-368

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8

Compiler-Assisted Memory Encryption for Embedded Processors
High performance embedded architectures and compilers; HiPEAC 2007
Nagarajan, V. ; Gupta, R. ; Krishnaswamy, A.
LECTURE NOTES INCOMPUTER SCIENCE. (4367):7-22

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9

MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing
High performance embedded architectures and compilers: HiPEAC 2008
Kissell, K.D.
LECTURE NOTES IN COMPUTER SCIENCE. (4917):9-21

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10

Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms
High performance embedded architectures and compilers; HiPEAC 2007
Hofstra, K. L. ; Gerez, S. H.
LECTURE NOTES INCOMPUTER SCIENCE. (4367):215-226

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11

Data Layout for Cache Performance on a Multithreaded Architecture
High performance embedded architectures and compilers
Sarkar, S. ; Tullsen, D.M.
LECTURE NOTES IN COMPUTER SCIENCE. (6590):43-68

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12

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
High performance embedded architectures and compilers
Farooq, M.U. ; John, L. ; Jacome, M.F.
LECTURE NOTES IN COMPUTER SCIENCE. (5409):324-338

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13

High Performance Processor Chips
Transactions on high performance embedded architectures and compilers 1
Wilkes, M. V.
LECTURE NOTES IN COMPUTER SCIENCE. (4050):1-4

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14

Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
High performance embedded architectures and compilers
Geiger, M. J. ; McKee, S. A. ; Tyson, G. S.
LECTURE NOTES IN COMPUTER SCIENCE. (3793):102-115

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15

XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs
High performance embedded architectures and compilers
Wu, G. ; Zhou, X. ; Lueh, G.-Y. ; et al.
LECTURE NOTES IN COMPUTER SCIENCE. (3793):130-152

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16

Cost-effective fixed-point hardware support for RISC-V embedded systems
Zoni, Davide ; Galimberti, Andrea
In Journal of Systems Architecture May 2022 126

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17

Compiler Support for Code Size Reduction Using a Queue-Based Processor
High performance embedded architectures and compilers; Transactions on high-performance embedded architectures and compilers II
Canedo, A. ; Abderazek, B. ; Sowa, M.
LECTURE NOTES IN COMPUTER SCIENCE. (5470):269-285

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18

Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories
High performance embedded architectures and compilers; Transactions on high-performance embedded architectures and compilers II
Mahoney, P. ; Savaria, Y. ; Bois, G. ; et al.
LECTURE NOTES IN COMPUTER SCIENCE. (5470):307-326

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19

autopin – Automated Optimization of Thread-to-Core Pinning on Multicore Systems ; Transactions on High-Performance Embedded Architectures and Compilers III
Klug, Tobias ; Ott, Michael ; Weidendorfer, Josef ; et al.

Buch

View record in Springer

20

Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
High performance embedded architectures and compilers; Transactions on high-performance embedded architectures and compilers II
Ahn, M. ; Paek, Y.
LECTURE NOTES IN COMPUTER SCIENCE. (5470):149-172

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