LEE, Yunsup, WATERMAN, Andrew, COOK, Henry, ZIMMER, Brian, KELLER, Ben, PUGGELLI, Alberto, KWAK, Jaehwa, JEVTIC, Ruzica, BAILEY, Stevo, BLAGOJEVIC, Milovan, CHIU, Pi-Feng, AVIZIENIS, Rimas, RICHARDS, Brian, BACHRACH, Jonathan, PATTERSON, David, ALON, Elad, NIKOLIC, Bora und ASANOVIC, Krste, 2016. An Agile Approach to Building RISC-V Microprocessors. IEEE Micro, Micro, IEEE. 1 März 2016. Vol. 36, no. 2, p. 8-20. DOI 10.1109/MM.2016.11.
Elsevier - Harvard (with titles)Lee, Y., Waterman, A., Cook, H., Zimmer, B., Keller, B., Puggelli, A., Kwak, J., Jevtic, R., Bailey, S., Blagojevic, M., Chiu, P.-F., Avizienis, R., Richards, B., Bachrach, J., Patterson, D., Alon, E., Nikolic, B., Asanovic, K., 2016. An Agile Approach to Building RISC-V Microprocessors. IEEE Micro, Micro, IEEE 36, 8-20. https://doi.org/10.1109/MM.2016.11
American Psychological Association 7th editionLee, Y., Waterman, A., Cook, H., Zimmer, B., Keller, B., Puggelli, A., Kwak, J., Jevtic, R., Bailey, S., Blagojevic, M., Chiu, P.-F., Avizienis, R., Richards, B., Bachrach, J., Patterson, D., Alon, E., Nikolic, B., & Asanovic, K. (2016). An Agile Approach to Building RISC-V Microprocessors. IEEE Micro, Micro, IEEE, 36(2), 8-20. https://doi.org/10.1109/MM.2016.11
Springer - Basic (author-date)Lee Y, Waterman A, Cook H, Zimmer B, Keller B, Puggelli A, Kwak J, Jevtic R, Bailey S, Blagojevic M, Chiu P-F, Avizienis R, Richards B, Bachrach J, Patterson D, Alon E, Nikolic B, Asanovic K (2016) An Agile Approach to Building RISC-V Microprocessors. IEEE Micro, Micro, IEEE 36:8-20. https://doi.org/10.1109/MM.2016.11
Juristische Zitierweise (Stüber) (Deutsch)Lee, Yunsup/ Waterman, Andrew/ Cook, Henry/ Zimmer, Brian/ Keller, Ben/ Puggelli, Alberto/ Kwak, Jaehwa/ Jevtic, Ruzica/ Bailey, Stevo/ Blagojevic, Milovan/ Chiu, Pi-Feng/ Avizienis, Rimas/ Richards, Brian/ Bachrach, Jonathan/ Patterson, David/ Alon, Elad/ Nikolic, Bora/ Asanovic, Krste, An Agile Approach to Building RISC-V Microprocessors, IEEE Micro, Micro, IEEE 2016, 8-20.