V, Santhosh und DESHPANDE, Abhay, 2025. Low Power Implementation of RISC V Processor with Fine Grained Clock Gating/Power Gating. In: . 20 November 2025.
Elsevier - Harvard (with titles)V, S., Deshpande, A., 2025. Low Power Implementation of RISC V Processor with Fine Grained Clock Gating/Power Gating, in: . https://doi.org/10.1109/CSITSS67709.2025.11295650
American Psychological Association 7th editionV, S., & Deshpande, A. (2025, November 20). Low Power Implementation of RISC V Processor with Fine Grained Clock Gating/Power Gating. https://doi.org/10.1109/CSITSS67709.2025.11295650
Springer - Basic (author-date)V S, Deshpande A (2025) Low Power Implementation of RISC V Processor with Fine Grained Clock Gating/Power Gating
Juristische Zitierweise (Stüber) (Deutsch)V, Santhosh/ Deshpande, Abhay, Low Power Implementation of RISC V Processor with Fine Grained Clock Gating/Power Gating, 2025, .