• FPGA-Based Hardware Accelerato...

Treffer: FPGA-Based Hardware Accelerator for Bottleneck Residual Blocks of MobileNetV2 Convolutional Neural Networks

Title:
FPGA-Based Hardware Accelerator for Bottleneck Residual Blocks of MobileNetV2 Convolutional Neural Networks
Authors:
Miro, Jordi P., Mohsin, Mokhles A., Alkamil, Arkan, Perera, Darshika G.
Source:
2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2025 IEEE 68th International Midwest Symposium on. :847-851 Aug, 2025
Relation:
2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS)
Database:
IEEE Xplore Digital Library