Treffer: Improving performance of HPC kernels on FPGAs using high-level resource management

Title:
Improving performance of HPC kernels on FPGAs using high-level resource management
Contributors:
Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. PM - Programming Models
Publisher Information:
Institute of Electrical and Electronics Engineers (IEEE)
Publication Year:
2023
Collection:
Universitat Politècnica de Catalunya, BarcelonaTech: UPCommons - Global access to UPC knowledge
Document Type:
Konferenz conference object
File Description:
1 p.; application/pdf
Language:
English
Relation:
https://ieeexplore.ieee.org/document/10171527; info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C22/ES/UPC-COMPUTACION DE ALTAS PRESTACIONES VIII/; http://hdl.handle.net/2117/406355
DOI:
10.1109/FCCM57271.2023.00041
Rights:
Open Access
Accession Number:
edsbas.E3E320B9
Database:
BASE

Weitere Informationen

In state-of-the-art FPGA, especially in chiplet-based devices, place and route has become an important challenge due to an increase in device size and complexity. In the same way, off-chip memory resources have grown in size and number of memory modules. Making efficient use of them has become a difficult task. ; This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative, by the Spanish Government (Grants PCI2021-121964 - TEXTAROSSA, PID2019-107255GB-C21, PID2019-107255GB-C22, MCIN/AEI/10.13039/501100011033, and CEX2021-001148-S), and by Generalitat de Catalunya (2021 SGR 01007). ; Peer Reviewed ; Postprint (author's final draft)