• Hardware Implementation of Pro...

Treffer: Hardware Implementation of Processor Allocation Schemes for Mesh-based Chip Multiprocessors

Title:
Hardware Implementation of Processor Allocation Schemes for Mesh-based Chip Multiprocessors
Authors:
Zydek, Dawid Maksymilian, Selvaraj, Henry
Source:
Electrical & Computer Engineering Faculty Research
Publisher Information:
Digital Scholarship@UNLV
Publication Year:
2010
Collection:
University of Nevada, Las Vegas: Digital Scholarship@UNLV
Subject Terms:
Algorithms--Data processing, Commuting--Energy consumption, Computer architecture, Microprocessors, Networks on a chip, Parallel computers, Computer and Systems Architecture, Computer Engineering, Controls and Control Theory, Electrical and Computer Engineering, Electrical and Electronics, Hardware Systems, Power and Energy, Signal Processing, Systems and Communications
Document Type:
Fachzeitschrift article in journal/newspaper
Language:
English
Relation:
https://digitalscholarship.unlv.edu/ece_fac_articles/273
Availability:
https://digitalscholarship.unlv.edu/ece_fac_articles/273
Accession Number:
edsbas.CB885352
Database:
BASE

Weitere Informationen

Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is driven by an Improved First Fit (IFF) algorithm, which is presented and described. Together with the proposed IFF technique, a new Improved Adaptive Scan (IAS) and an Improved Quick Allocation (IQA) algorithms are introduced and discussed and compared with previously known important techniques. The presented synthesis results reveal that the proposed PA achieves good frequency results while, at the same time is characterized by low logic utilization.