Treffer: FPGA-based coherent doppler processor for marine radar applications

Title:
FPGA-based coherent doppler processor for marine radar applications
Source:
Graduate Theses and Dissertations
Publisher Information:
eCommons
Publication Year:
2016
Document Type:
Fachzeitschrift text
Language:
unknown
Rights:
undefined
Accession Number:
edsbas.15D83A38
Database:
BASE

Weitere Informationen

The goal of this research is to develop a method for affordable and reliable sampling and coherent processing of measurement data collected via a modified magnetron oscillator based marine radar system. Non-coherent low-priced marine radar systems offer limited surveillance in clutter rich environments as compared to more expensive and complex coherent solid state radar systems. The approach used herein leverages modern analog to digital converters (ADC) and field programmable gate array (FPGA) technology to affordably and effectively sample the radiated and received signals for further analysis using FFT-based Doppler processing or cross correlation analysis. Track processing of moving targets is fundamental to any advanced radar and is a further focus of this research. The marine radar hardware is modified to capture the transmit signal at the source, and the receive signal at the aperture, for processing via FPGAs. The receive pulse train is cross-correlated with the transmit pulse train reference to remove the uncertainties in the phase history of the collected data. This operation ultimately makes the radar fully coherent on receive. Once the receive signal is made coherent, classical Doppler processing is used to differentiate moving targets from clutter and electromagnetic interference. A real time system has been built on a board with ADCs, FPGAs, and a microprocessor. Mixing of the Transmit (TX) and the Receive (RX) signals, Fourier transform analysis, and Pulse Compression are all executed digitally in the FPGA whereas Doppler Processing is performed on the microprocessor. This paper presents the underlying principles of cohering signals on receive, and it will show a real-time implementation of such algorithms using FPGAs.