SINGH BAJWA, R., OWENS, R.M. und IRWIN, M.J., 1994. Area time trade-offs in micro-grain VLSI array architectures. IEEE Transactions on Computers. 10 Januar 1994. Vol. 43, no. 10, p. 1121-1128. DOI 10.1109/12.324538.
Elsevier - Harvard (with titles)Singh Bajwa, R., Owens, R., Irwin, M., 1994. Area time trade-offs in micro-grain VLSI array architectures. IEEE Transactions on Computers 43, 1121-1128. https://doi.org/10.1109/12.324538
American Psychological Association 7th editionSingh Bajwa, R., Owens, R., & Irwin, M. (1994). Area time trade-offs in micro-grain VLSI array architectures. IEEE Transactions on Computers, 43(10), 1121-1128. https://doi.org/10.1109/12.324538
Springer - Basic (author-date)Singh Bajwa R, Owens R, Irwin M (1994) Area time trade-offs in micro-grain VLSI array architectures.. IEEE Transactions on Computers 43:1121-1128. https://doi.org/10.1109/12.324538
Juristische Zitierweise (Stüber) (Deutsch)Singh Bajwa, R./ Owens, R.M./ Irwin, M.J., Area time trade-offs in micro-grain VLSI array architectures., IEEE Transactions on Computers 1994, 1121-1128.