ISO-690 (author-date, English)

SHIVA, G. Ashwin und PATIL, Mangal, 2025. "Dynamic Voltage Scaling For Low-Power VLSI Design: A Review Of Power Optimization Techniques And Memory Efficiency Enhancements". International Journal of Environmental Sciences (2229-7359). 16 August 2025. Vol. 11, , p. 7672-7685. DOI 10.64252/3 pyf9 k26.

Elsevier - Harvard (with titles)

Shiva, G.A., Patil, M., 2025. "Dynamic Voltage Scaling For Low-Power VLSI Design: A Review Of Power Optimization Techniques And Memory Efficiency Enhancements". International Journal of Environmental Sciences (2229-7359) 11, 7672-7685. https://doi.org/10.64252/3 pyf9 k26

American Psychological Association 7th edition

Shiva, G. A., & Patil, M. (2025). "Dynamic Voltage Scaling For Low-Power VLSI Design: A Review Of Power Optimization Techniques And Memory Efficiency Enhancements". International Journal of Environmental Sciences (2229-7359), 11, 7672-7685. https://doi.org/10.64252/3 pyf9 k26

Springer - Basic (author-date)

Shiva GA, Patil M (2025) "Dynamic Voltage Scaling For Low-Power VLSI Design: A Review Of Power Optimization Techniques And Memory Efficiency Enhancements".. International Journal of Environmental Sciences (2229-7359) 11:7672-7685. https://doi.org/10.64252/3 pyf9 k26

Juristische Zitierweise (Stüber) (Deutsch)

Shiva, G. Ashwin/ Patil, Mangal, "Dynamic Voltage Scaling For Low-Power VLSI Design: A Review Of Power Optimization Techniques And Memory Efficiency Enhancements"., International Journal of Environmental Sciences (2229-7359) 2025, 7672-7685.

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