A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs. - MAHANI, NEGIN (SADAT) (NEMATOLLAHI); FALAHATI, HAJAR; DARABI, SINA; JAVADI-NEZHAD, AHMAD; YUNHO OH; SADROSADATI, MOHAMMAD; SARBAZI-AZAD, HAMID; FALSAFI, BABAK (ACM Transactions on Architecture & Code Optimization, 2025)