MAHANI, NEGIN (SADAT) (NEMATOLLAHI), FALAHATI, HAJAR, DARABI, SINA, JAVADI-NEZHAD, AHMAD, YUNHO OH, SADROSADATI, MOHAMMAD, SARBAZI-AZAD, HAMID und FALSAFI, BABAK, 2025. A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs. ACM Transactions on Architecture & Code Optimization. 1 September 2025. Vol. 22, no. 3, p. 1-27. DOI 10.1145/3760782.
Elsevier - Harvard (with titles)MAHANI, N. (SADAT) (NEMATOLLAHI), FALAHATI, H., DARABI, S., JAVADI-NEZHAD, A., YUNHO OH, SADROSADATI, M., SARBAZI-AZAD, H., FALSAFI, B., 2025. A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs. ACM Transactions on Architecture & Code Optimization 22, 1-27. https://doi.org/10.1145/3760782
American Psychological Association 7th editionMAHANI, N. (SADAT) (NEMATOLLAHI), FALAHATI, H., DARABI, S., JAVADI-NEZHAD, A., YUNHO OH, SADROSADATI, M., SARBAZI-AZAD, H., & FALSAFI, B. (2025). A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs. ACM Transactions on Architecture & Code Optimization, 22(3), 1-27. https://doi.org/10.1145/3760782
Springer - Basic (author-date)MAHANI N (SADAT) (NEMATOLLAHI), FALAHATI H, DARABI S, JAVADI-NEZHAD A, YUNHO OH, SADROSADATI M, SARBAZI-AZAD H, FALSAFI B (2025) A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs.. ACM Transactions on Architecture & Code Optimization 22:1-27. https://doi.org/10.1145/3760782
Juristische Zitierweise (Stüber) (Deutsch)MAHANI, NEGIN (SADAT) (NEMATOLLAHI)/ FALAHATI, HAJAR/ DARABI, SINA/ JAVADI-NEZHAD, AHMAD/ YUNHO OH/ SADROSADATI, MOHAMMAD/ SARBAZI-AZAD, HAMID/ FALSAFI, BABAK, A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs., ACM Transactions on Architecture & Code Optimization 2025, 1-27.