• Suche: LUCAS associative array processor

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Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and Reliability.
Venkatesha, Shashikiran ; Parthasarathi, Ranjani
ACM Computing Surveys. Nov2024, Vol. 56 Issue 11, p1-76. 76p.

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STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs.
CARDOSO DE LIMA, JOÃO PAULO ; BRANDALERO, MARCELO ; HÜBNER, MICHAEL ; et al.
ACM Journal on Emerging Technologies in Computing Systems; Dec2021, Vol. 18 Issue 2, p1-22, 22p

VON Neumann, John, 1903-... ARCHITECTURAL design VERNACULAR architecture ARRAY processing FINITE state machines ASSOCIATIVE storage
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Programming FPGAs for economics: An introduction to electrical engineering economics.
Cheela, Bhagath ; DeHon, André ; Fernández‐Villaverde, Jesús ; et al.
Quantitative Economics. Jan2025, Vol. 16 Issue 1, p49-87. 39p.

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Towards high scalability and fine-grained parallelism on distributed HPC platforms.
de Haro ruiz, Juan Miguel ; Álvarez Martínez, Carlos ; Jiménez-González, Daniel ; et al.
ACM Transactions on Architecture & Code Optimization; Dec2025, Vol. 22 Issue 4, p1-22, 22p

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A GPU-CUDA Numerical Algorithm for Solving a Biological Model.
De Luca, Pasquale ; Fiorillo, Giuseppe ; Marcellino, Livia
AppliedMath; Dec2025, Vol. 5 Issue 4, p178, 24p

NVIDIA Corp. GRAPHICS processing unit... NUMERICAL analysis PARALLEL programming BIOLOGICAL models QUANTITATIVE research …
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A neuromorphic processor with on-chip learning for beyond-CMOS device integration.
Greatorex, Hugh ; Richter, Ole ; Mastella, Michele ; et al.
Nature Communications; 7/11/2025, Vol. 16 Issue 1, p1-14, 14p

NEUROMORPHICS SYSTEM integration BIOLOGICALLY inspired co... ARTIFICIAL neural networ... TECHNOLOGICAL innovation...
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Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM.
Grossi, Alessandro ; Vianello, Elisa ; Zambelli, Cristian ; et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Dec2018, Vol. 26 Issue 12, p2599-2607, 9p

NONVOLATILE random-acces... ASSOCIATIVE storage HAFNIUM oxide
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DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor.
THIEU, GIA BAO ; GESPER, SVEN ; PAYÁ-VAYÁ, GUILLERMO
ACM Transactions on Architecture & Code Optimization; Jun2025, Vol. 22 Issue 2, p1-25, 25p

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Associative Graph Processor and Its Properties.
Nepomniaschaya, A. ; Kokosinski, Z.
2004 International Conference on Parallel Computing in Electrical Engineering; 2004, p297-302, 6p

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Unraveling the dynamics of seizure-like activity in neuronal networks using machine learning.
Mufti, Shatha J. ; Verma, Shourya ; Martinez, Jhon ; et al.
Journal of Neurophysiology; Dec2025, Vol. 134 Issue 6, p1-25, 25p

SEIZURES (Medicine) MACHINE learning DIMENSIONAL reduction al... NEURAL circuitry ANTICONVULSANTS SYSTEM dynamics
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Astrocyte-Mediated Plasticity: Multi-Scale Mechanisms Linking Synaptic Dynamics to Learning and Memory.
Yamamoto, Masaya ; Takano, Tetsuya
Cells (2073-4409); Dec2025, Vol. 14 Issue 24, p1936, 25p

ASTROCYTES MEMORY NEUROGLIA SYNAPSES LEARNING INTRACELLULAR calcium …
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Technique for Transforming Discrete Optimization Problems into QUBO Form.
Semenov, A. M. ; Usmanov, S. R. ; Fedorov, A. K.
Problems of Information Transmission; Sep2025, Vol. 61 Issue 2, p110-142, 33p

GRAPH theory COMBINATORIAL optimizati... LINEAR matrix inequaliti... QUADRATIC programming BOOLEAN expressions DATA structures
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Neural networks with quantum states of light.
Labay-Mora, Adrià ; García-Beni, Jorge ; Giorgi, Gian Luca ; et al.
Philosophical Transactions of the Royal Society A: Mathematical, Physical & Engineering Sciences; 12/30/2024, Vol. 382 Issue 2287, p1-24, 24p

QUANTUM optics QUANTUM computing QUANTUM theory ARTIFICIAL neural networ... QUANTUM states
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HDRLPIM: A Simulator for Hyper-Dimensional Reinforcement Learning Based on Processing In-Memory.
Rakka, Mariam ; Amer, Walaa ; Chen, Hanning ; et al.
ACM Journal on Emerging Technologies in Computing Systems; Oct2024, Vol. 20 Issue 4, p1-17, 17p

REINFORCEMENT learning MEMORY ENCODING
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Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors.
Dai, Jianwei ; Guan, Menglong ; Wang, Lei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Feb2014, Vol. 22 Issue 2, p396-407, 12p

CACHE memory ENERGY consumption ARRAY processors BENCHMARK testing (Engin... LOGIC circuits LOW voltage integrated c...
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Synchronous Deterministic Parallel Programming for Multi-Cores with ForeC.
YIP, EUGENE ; GIRAULT, ALAIN ; ROOP, PARTHA S. ; et al.
ACM Transactions on Programming Languages & Systems. Jun2023, Vol. 45 Issue 2, p1-74. 74p.

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Area time trade-offs in micro-grain VLSI array architectures.
Singh Bajwa, R. ; Owens, R.M. ; Irwin, M.J.
IEEE Transactions on Computers; 1994, Vol. 43 Issue 10, p1121-1128, 8p

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Matrix multiplication on LUCAS.
Ohlsson, Lennart ; Svensson, Bertil
1983 IEEE 6th Symposium on Computer Arithmetic (ARITH); 1/ 1/1983, p116-122, 7p

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Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing.
Karunaratne, Geethan ; Le Gallo, Manuel ; Hersche, Michael ; et al.
IEEE Transactions on Circuits & Systems. Part II: Express Briefs; May2021, Vol. 68 Issue 5, p1725-1729, 5p

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