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A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications
Kasgen, Philipp S. ; Weinhardt, Markus ; Hochberger, Christian
2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ReConFigurable Computing and FPGAs (ReConFig), 2018 International Conference on. :1-4 Dec, 2018
A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications
Kulkarni, Amit ; Vasteenkiste, Elias ; Stroobandt, Dirk ; et al.
2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) Parallel and Distributed Processing Symposium Workshops, 2016 IEEE International. :265-270 May, 2016
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
Melchert, J. ; Zhang, K. ; Mei, Y. ; et al.
IEEE Computer Architecture Letters IEEE Comput. Arch. Lett. Computer Architecture Letters. 22(1):45-48 Jan, 2023
Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution
Lee, Ganghee ; Chang, Kyungwook ; Choi, Kiyoung
2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on. :1-4 Apr, 2010
Mapping control intensive kernels onto coarse-grained reconfigurable array architecture
Kyungwook Chang ; Choi, Kiyoung
2008 International SoC Design Conference SoC Design Conference, 2008. ISOCC '08. International. 01:I-362-I-365 Nov, 2008
CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications
Le, V.T.D. ; Pham, H.L. ; Tran, T.H. ; et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 44(5):1793-1806 May, 2025
An Analysis of Mapping Polybench Kernels to HPC CGRAs
Weinhardt, Markus
2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) IPDPSW Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2022 IEEE International. :647-654 May, 2022
Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications
Kulkarni, Amit ; Stroobandt, Dirk ; Werner, Andre ; et al.
3DRA: Dynamic Data-Driven Reconfigurable Architecture
Lee, J. ; Amornpaisannon, B. ; Diavastos, A. ; et al.
IEEE Access Access, IEEE. 11:105288-105298 2023
The research of interconnection network on coarse-grained reconfigurable Cipher Logic Array
Li, Yuanming ; Yan, Yinjian ; Li, Wei ; et al.
2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC) Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), 2017 IEEE 2nd. :1046-1051 Mar, 2017
A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory
Silva, Victor ; Fernandes, Jorge R. ; Vestias, Mario P. ; et al.
2012 International Conference on Reconfigurable Computing and FPGAs Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. :1-6 Dec, 2012
SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing
Patel, Kunjan ; McGettrick, Séamas ; Bleakley, Chris J.
2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on. :109-112 May, 2011
CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance
Yang, Chen ; Hou, Jia ; Wang, Yizhou ; et al.
2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Electronics, Circuits and Systems (ICECS), 2019 26th IEEE International Conference on. :107-108 Nov, 2019
Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design
Deng, J. ; Tang, X. ; Zhang, J. ; et al.
IEEE Transactions on Computers IEEE Trans. Comput. Computers, IEEE Transactions on. 74(1):185-199 Jan, 2025
Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures
Das, Satyajit ; Martin, Kevin J. M. ; Coussy, Philippe ; et al.
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific. :127-132 Jan, 2017
RAW 2024 Invited Talk-6: Reconfigurable Architectures for High-Performance Computing
Sano, Kentaro
2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) IPDPSW Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2024 IEEE International. :88-88 May, 2024
CREPE: Concurrent Reverse-Modulo-Scheduling and Placement for CGRAs
Sunny, C. ; Das, S. ; Martin, K.J.M. ; et al.
IEEE Transactions on Parallel and Distributed Systems IEEE Trans. Parallel Distrib. Syst. Parallel and Distributed Systems, IEEE Transactions on. 35(7):1293-1306 Jul, 2024
Generating CGRA Processing Element Hardware with CGRAgen
Damsgaard, Hans Jakob ; Ometov, Aleksandr ; Nurmi, Jari
2023 26th Euromicro Conference on Digital System Design (DSD) DSD Digital System Design (DSD), 2023 26th Euromicro Conference on. :1-7 Sep, 2023
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
High performance embedded architectures and compilers: HiPEAC 2008
Bouwens, F. ; Berekovic, M. ; De Sutter, B. ; et al.
LECTURE NOTES IN COMPUTER SCIENCE. (4917):66-81
Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane
Deng, Jinyi ; Tang, Xinru ; Zhang, Jiahao ; et al.
2023 56th IEEE/ACM International Symposium on Microarchitecture (MICRO) Microarchitecture (MICRO), 2023 56th IEEE/ACM International Symposium on. :1395-1408 Oct, 2023
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